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| 2N6896 Data Sheet December 2001 -6A, -100V, 0.600 Ohm, P-Channel Power MOSFET The 2N6896 is a P-Channel enhancement mode silicon gate power MOS field effect transistor designed for high-speed applications such as switching regulators, switching converters, relay drivers, and drivers for high power bipolar switching transistors. Features * -6A, -100V * rDS(ON) = 0.600 * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Ordering Information PART NUMBER 2N6896 PACKAGE TO-204AA BRAND 2N6896 * Majority Carrier Device * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" NOTE: When ordering, include the entire part number. Symbol D G S Packaging JEDEC TO-204AA DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) (c)2001 Fairchild Semiconductor Corporation 2N6896 Rev. B 2N6896 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified 2N6896 -100 -100 -6 -20 20 60 0.48 -55 to 150 300 260 UNITS V V A A V W W/oC oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 1M) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 0.25mA VDS = -80V VDS = -80V, TC = 125oC MIN -100 -2 1 200 100 40 ID = 3.8A, VDS = -50V RGEN = RGS = 15, VGS = -10V TYP MAX -4 1 50 100 2.28 -6 0.600 0.960 4 800 350 150 60 100 150 100 2.083 UNITS V V A A nA V V S pF pF pF ns ns ns ns oC/W Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero-Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On-Voltage (Note 2) IGSS VDS(ON) VGS = 20V, VDS = 0V ID = 3.8A, VGS = -10V ID = 6A, VGS = -10V Drain to Source On Resistance (Note 2) rDS(ON) ID = 3.8A, VGS = -10V ID = 3.8A, VGS = 10V, TC = 125oC Forward Transconductance (Note 2) Input Capacitance Output Capacitance Reverse-Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Thermal Resistance Junction to Case gfs CISS COSS CRSS td(ON) tr td(OFF) tf RJC ID = 3.8A, VDS = -10V VGS = 0V, VDS = -25V f = 0.1MHz Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulsed: Pulse duration = 300s, max, duty cycle = 2%. 3. Repetitive Rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr TEST CONDITIONS ISD = 12A ISD = 4A, dISD/dt = 50A/s MIN 0.8 TYP MAX 1.6 375 UNITS V ns (c)2001 Fairchild Semiconductor Corporation 2N6896 Rev. B 2N6896 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 10s ID, DRAIN CURRENT (A) 0.8 10 100s 1.0ms 10ms 100ms DC Unless Otherwise Specified 100 TC = 25oC TJ = MAX RATED 0.6 0.4 1 OPERATION IN THIS AREA LIMITED BY rDS(ON) VDSS (MAX) = 100V 0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 0.01 1 10 100 VDS, DRAIN TO SOURCE (V) 1000 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. FORWARD BIAS OPERATING AREAS Id(ON), ON-STATE DRAIN CURRENT (A) 16 14 12 10 8 6 4 2 rDS(ON), DRAIN TO SOURCE ON RESISTANCE () VDS = -10V PULSE TEST PULSE DURATION = 80s DUTY CYCLE 2% 0.8 -40oC 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 VGS = -10V PULSE TEST PULSE DURATION = 80s DUTY CYCLE 2% 12 14 16 18 20 25oC -40oC 125oC 25oC 125oC 0 -2 -4 -6 -8 -10 VGS, GATE TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) FIGURE 3. TRANSFER CHARACTERISTICS FIGURE 4. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT 3 NORMALIZED ON RESISTANCE ID = 3.8A VGS = 10V THRESHOLD VOLTAGE (V) NORMALIZED GATE 1.5 ID = 0.25mA VDS = VGS 2 1.0 1 0.5 0 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 150 0.5 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 150 FIGURE 5. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 6. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation 2N6896 Rev. B 2N6896 Typical Performance Curves 800 700 C, CAPACITANCE (pF) 600 500 400 300 200 100 0 -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) COSS CRSS -50 CISS gfs, TRANSCONDUCTANCE (S) Unless Otherwise Specified (Continued) f = 1MHz 8 7 6 5 4 3 2 1 0 125oC -40oC 25oC VDS = 10V PULSE TEST PULSE DURATION = 80s DUTY CYCLE 2% 0 1 2 3 4 5 6 7 ID, DRAIN CURRENT (A) 8 9 10 FIGURE 7. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 8. TRANSCONDUCTANCE vs DRAIN CURRENT Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL 0 10% tOFF td(OFF) tf 10% DUT VGS RG VDD + VDS VGS 0 90% 90% 10% 50% PULSE WIDTH 90% 50% FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS (c)2001 Fairchild Semiconductor Corporation 2N6896 Rev. B 2N6896 Test Circuits and Waveforms CURRENT REGULATOR (Continued) -VDS (ISOLATED SUPPLY) 0 VDS DUT 12V BATTERY 0.2F 50k 0.3F Qgs D G 0 IG(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0 DUT VDD Qgd VGS Qg(TOT) IG(REF) FIGURE 13. GATE CHARGE TEST CIRCUIT FIGURE 14. GATE CHARGE WAVEFORMS (c)2001 Fairchild Semiconductor Corporation 2N6896 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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